pynq_to_zynq

Loopback Project Step 2: The System Integration

1. The Goal

To create a complete hardware system that connects the Zynq Processing System (PS) to your custom math_accelerator IP block via the AXI interconnect.

By the end of this step, we will generate the Bitstream (which configures the FPGA) and the XSA File (Xilinx Support Archive), which tells the software layer exactly how the hardware is wired.

2. Sanity Check (Pre-Flight)

Before proceeding, ensure you have the output from Step 1.

• IP Repository: You have a folder (e.g., C:/pynq_work/ip_repo) containing the math_accelerator_1.0 folder.
• XML Descriptor: Inside that folder, component.xml exists.
• Vivado: You are ready to create a fresh project (close the temporary IP generation project if it’s still open).

3. Step-by-Step Instructions

Part A: Project Setup & IP Import

1. Create New Project:
   • Open Vivado > Create Project.
   • Name: loopback_system.
   • Location: C:/pynq_work/projects (Keep path lengths short!).
   • Type: RTL Project (Do not specify sources yet).
   • Part/Board: Select PYNQ-Z2 (search “pynq” in the boards tab).
   • Click Finish.
2. Add IP Repository:
   • In the Flow Navigator (left), click Settings.
   • Navigate to IP > Repository.
   • Click the + (Plus) button.
   • Select your C:/pynq_work/ip_repo folder.
   • Check: Vivado should popup a message saying “1 Repository, 1 IP” found. If it says 0, you selected the wrong folder level.
   • Click Apply > OK.

Part B: The Block Design

This is where we wire the chip.

1. Create Block Design:
   • In Flow Navigator, click Create Block Design.
   • Name: system_design.
   • Click OK.
2. Add the Processor:
   • Right-click the white canvas > Add IP.
   • Search for ZYNQ7 Processing System. Double-click to add.
   • Check: You should see the Zynq block. It might look “generic” initially.
3. Run Block Automation (Crucial):
   • A green banner will appear at the top: “Designer Assistance available. Run Block Automation”.
   • Click Run Block Automation.
   • Ensure “Apply Board Preset” is checked. This configures the DDR memory timings and Clocks specifically for the PYNQ-Z2.
   • Click OK.
   • Check: The Zynq block input pins (DDR, FIXED_IO) should now have names, representing external pin connections.
4. Add Your Custom IP:
   • Right-click canvas > Add IP.
   • Search for math_accelerator.
   • Double-click to add.
   • Check: You now have a “math_accelerator_0” block floating on the canvas.

Part C: Wiring (The “Magic” Button)

We need to connect the high-speed AXI bus, the resets, and the clocks.

1. Run Connection Automation:
   • The green banner appears again: “Designer Assistance available. Run Connection Automation”.
   • Click Run Connection Automation.
   • Check the box for /math_accelerator_0/S00_AXI.
   • Options: verify that “Master” is set to /processing_system7_0/M_AXI_GP0.
   • Click OK.
2. Inspect the Result:
   • Vivado has automatically added two new critical blocks:
     • Processor System Reset: Handles synchronizing the reset signal.
     • AXI Interconnect: A “switch” that routes traffic from the CPU to your IP.
   • Click the Regenerate Layout button (blue circular arrow in the toolbar) to clean up the messy wires.

Part D: Addressing

We need to know where our IP lives in the memory map.

1. Open Address Editor:
   • Click the Address Editor tab (usually next to the “Diagram” tab above the canvas).
   • Find math_accelerator_0.
   • Offset Address: Note this value! It usually defaults to 0x43C00000.
   • Action: If it says “Unmapped”, right-click and select “Assign Address”.
   • Record this number. You will need it for your C code in Step 4.

Part E: Output Generation

Now we compile the design.

1. Validate Design:
   • Press F6 or click Tools > Validate Design.
   • Check: Ensure you get “Validation Successful”. Warnings are okay; Errors are not.
2. Create HDL Wrapper:
   • In the Sources tab (left), find system_design (the block design file).
   • Right-click it > Create HDL Wrapper.
   • Select Let Vivado manage wrapper and auto-update.
   • Click OK.
   • Reason: The block design is a schematic; Vivado needs a top-level Verilog file to start synthesis.
3. Generate Bitstream:
   • In Flow Navigator, click Generate Bitstream.
   • Click Yes to launch Synthesis and Implementation.
   • Wait: This takes 10-20 minutes depending on your PC.
   • Success: A dialog box will appear saying “Bitstream Generation Completed”. Click Cancel (we don’t need to open the Hardware Manager).

Part F: Export Hardware (The Handoff)

We need to bundle everything for PetaLinux.

1. Export XSA:
   • Go to File > Export > Export Hardware.
   • Click Next.
   • Output: Select Include bitstream. (Critical! If you miss this, the FPGA won’t get programmed).
   • Files Name: system_design_wrapper (default is fine).
   • Export Location: Choose a path (e.g., C:/pynq_work/output).
   • Click Finish.

4. Final Validation

Did Step 2 work?

1. Navigate to your export folder (C:/pynq_work/output).
2. Look for system_design_wrapper.xsa.
3. Check file size: It should be roughly 5 MB to 10 MB.
   • Failure Mode: If it is ~500 KB, you likely forgot to select “Include Bitstream” during export.

5. Recap: What did we just do?

• System Assembly: We didn’t just write code; we built a computer. We connected a dual-core ARM CPU to a custom Arithmetic Logic Unit (ALU) we designed.
• AXI Interconnect: We used the AXI GP (General Purpose) port. We learned that Vivado handles the complex bus arbitration logic for us via “Connection Automation”.
• Memory Mapping: We established that physical address 0x43C00000 is now hard-wired to our custom Adder logic.

Next Step: In Step 3, we leave the comfortable GUI of Vivado and enter the Linux terminal to build the OS that runs on this hardware.

6. Next Step

The hardware is defined. Now we need an Operating System to manage it.

Go to Step 3: The Embedded Linux Build

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